1. Field of the Invention
This invention relates generally to the field of memory logic devices and more specifically to systems and method for testing memory devices. More particularly, the present invention relates to memory arrays that include circuitry for testing multiple port memory arrays.
2. Description of the Background Art
Memory devices are well known in the semiconductor industry. The integration of memory cores with other circuitry has increased dramatically because of the proliferation and popularity of Application Specific Integrated Circuits (ASIC). New and improved designs for memory arrays such for system on a chip have increased the demand for shorter access times and greater word sizes. Since the memory cores are now integrated with other circuitry, a faulty memory core causes the entire chip to be defective and worthless. Thus, there is a need for a more reliable system and method for testing memory devices and protecting against such failures.
One prior art approach is to include circuitry for testing the memory as part of the memory device itself. This circuitry is used once for testing when the chip is fabricated, and then remains unused during normal operation of the memory device. Thus, it is preferred to minimize the area required for such testing circuitry. Furthermore, new memory arrays have ever-decreasing size and power requirements. For example, new uses for ASICs such as cellular telephones, portable computers, and hand held devices require new memory arrays that are more powerful, yet require less circuit area to implement and consume less power for increased battery life. Therefore, the space available for providing circuitry for testing the memory array on the integrated circuit itself is severely limited. Thus, there is very little excess area to provide circuitry for testing of the memory device as part of the integrated circuit.
Multiple port memory devices pose a particular problem for adequate and accurate testing. Because of the multiple ports, there are certain conditions or states for a multiple port memory device that place additional stress on the integrated circuit, and are therefore, more likely to cause failure. One particular situation is shown in FIG. 1. FIG. 1 illustrates part of a prior art memory array 20 showing portions of the circuit likely to fail if not properly tested. A exemplary memory cell 22 formed from a pairs of transistors 10, 11, 12, 13 and its coupling to word lines WLA, WLB and bit lines BLA, BLB, BLAB, BLBB are shown. FIG. 1 also illustrates relevant portions of a pre-chargeing circuit 50 that include pre-charging transistors 14, 16 for the respective bit lines BLA, BLB and an input control line coupled to inverter 15. The pre-charging transistors 14, 16 are controlled by a control signal, EQ. In normal operation, the memory cell 22 will have the one word line, WLA, active and the other word line, WLB, inactive (or vice versa). Standard operation of the memory cell 22 will test such a case, and the read current (.apprxeq.200 .mu.A shown as line 18) will be sufficient for the sense amplifiers to operate correctly, thus the memory device will be operational. However, a more significant case, and a case where the transistor 12 forming the cell 22 undergoes more significant stress is where both the word lines WLA, WLB are active. In this case, the read current is reduced to approximately (.apprxeq.150 .mu.A) because it is distributed over two bit lines. This current may be insufficient to allow the sense amplifier to operate properly, and thus, the memory cell 22 will be defective in such instances. This is a worse case test for the memory cells 22 that often goes untested, because the controller typically has no way to assert both the word lines WLA, WLB simultaneously. In the normal case, it is difficult to have both word lines active simultaneously or to guarantee that that both word lines will be enabled at the same time during normal mode to allow worst case testing. Thus, there is a need for a system and method that can properly test and detect circuit failures of this type.
Another concern when both lines are pre-charged and providing current is the effect on reliability of circuit. If the current is increased and the circuit has not been properly constructed or processed, then a contact may fail such as due to a break in the metal layer. There are sometimes defects in the integrated circuit that will operate properly under normal conditions, however, under stressful conditions a contact or metal line will break. Such defects remain in the chip and will not be detected until after the chips are shipped. Later during normal operations, the defects will be revealed due to clock skew or accessing both WLA and WLB simultaneously.
Referring now to FIG. 2, yet another part of a prior art memory array 20 showing other portions of the circuit likely to fail is shown. For ease of understanding and convenience, FIG. 2 illustrates only the relevant portions of FIG. 1. The memory cell 22 is coupled to respective word line transistors 24, 26. In certain instances, the word line WLA may be active in reading the line and word line WLB may be active in writing the line. In such a case the path for the current indicated by arrow 28. This places additional stress on the transistors 10, 12 because the line must sink the current from both word lines WLA, WLB. Furthermore, when word line WLA is trying to write, the current from the pre-charging of WLB for read may be too strong and writing to WLA may not work (e.g., may not exceed the necessary threshold). This shows another area where the memory cells 22 of the prior art are not tested.
As noted above, one common problem with existing memory cores is that these circumstances discussed above with reference to FIGS. 1 and 2 often are brought into existence because of clock skew. FIG. 3 illustrates how skew of the clock signals used in the memory core can occur. While FIG. 3 describes a particular example where the clk.sub.A input and the clk.sub.B input of the circuit receive the same clock signal even though it is skewed by the time it reaches these inputs, the presence of clock skew applies equally if not more for situations where the clk.sub.A input and the clk.sub.B input receive different clock signals. First, there is clock skew internal to the memory core as shown by lines 34, 36 since lengths of the word lines will be different due to the position of the respective control, pre-decoding and X-decoding logic. Thus, depend on your position in the memory, the clock skew may differ dramatically. Second, there will be external skew. Since each control portion of the core, Control.sub.A, Control.sub.B, has its own clock signal clk.sub.A, clk.sub.B that has a different path 30, 32 and must traverse different portions of the circuit. Thus, the clock skew of a core will also vary radically depending on the other circuitry to which the memory core is coupled and the different paths that the clock signal must traverse. Therefore, the memory core if not tested for the condition identified above with reference to FIGS. 1 and 2, may fail because they are used with different implementations of circuitry having different clock skew. In the prior art, even if the ports are accessed at the same time, there is no way to be sure that the above conditions are tested in normal operation because of clock skew. In other words, the prior art has not capability to reproduce and test for clock skew. For example, if the memory is designed and tested under a specific clock skew it may pass. Subsequently, the same memory used in a different application with a different clock skew may fail.
Therefore, there is a need for systems and method for testing multiple port memory devices that effectively test the most stressful conditions and accounts for clock skew.